Ralph Halbach

IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA

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Identification and verification of BEOL metal fails due to ESD stress using current density analysis tool

Souvick Mitra,Nicholas Palmer,Mujahid Muhammad,Robert J Gauthier,Ralph Halbach, Christopher Seguin

Electrical Overstress/Electrostatic Discharge Symposium, pp.1-6, (2013)

EIWOSBibtex

Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network

You Li,James Di Sarro,Shunhua Chang, Junjun Li,Robert J Gauthier,Ralph Halbach

Electrical Overstress/Electrostatic Discharge Symposium, pp.1-8, (2013)

Cited by2EIWOSBibtex

A current density analysis tool to identify BEOL fails under ESD stress

Souvick Mitra,Nicholas Palmer,Robert J Gauthier,Mujahid Muhammad,Ralph Halbach, C Seguin

Electrical Overstress/Electrostatic Discharge Symposium, pp.1-6, (2011)

Cited by7EIWOSBibtex

Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

Souvick Mitra,Robert J Gauthier,Shunhua Chang,Junjun Li,Ralph Halbach, C Seguin

Electrical Overstress/ Electrostatic Discharge Symposium, pp.1-6E, (2010)

Cited by12EIWOSBibtex

Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

David Alvarez,Kiran Chatty,Christian Russ,Michel J. Abou-Khalil,Junjun Li,Robert Gauthier,Kai Esmark,Ralph Halbach,Christopher Seguin

Microelectronics Reliability, no. 12 (2009): 1417-1423

Cited by16EIBibtex

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

David Alvarez,Kiran V. Chatty,Christian Russ,Michel J. Abou-Khalil,Junjun Li,Robert Gauthier,Kai Esmark,Ralph Halbach,Christopher Seguin

Microelectronics Reliability, no. 12 (2009): 1417-1423

Cited by9EIBibtex

ESD protection using grounded gate, gate non-silicided (GG-GNS) ESD NFETs in 45nm SOI technology

Sanjit K Mitra,Robert C Gauthier,Junjun Li,Michel J Aboukhalil,Christopher S Putnam,R Halbach,Christopher Seguin

Tucson, AZ, pp.312-316E, (2008)

Cited by14EIWOSBibtex

On The Interaction of ESD, NBTI and HCI in 65nm Technology

Rahul Mishra,Sanjit K Mitra,Robert J Gauthier,Dimitris E Ioannou,Dimitris Kontos,Kiran V Chatty,Christel Seguin,Ralph Halbach

Phoenix, AZ, pp.17-22E, (2007)

Cited by13EIWOSBibtex

External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies

Dimitris Kontos,Robert J Gauthier,Kiran V Chatty, K Domanskr,Mujahid Muhammad,Christopher Seguin,Ralph Halbach

(2007)

Bibtex

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

Dimitris Kontos,Krzysztof Domanski,Robert J Gauthier,Kiran V Chatty,Mujahid Muhammad,Christopher Seguin,Ralph Halbach,Christian Russ,David A Alvarez

San Jose, CA, pp.145-150E, (2006)

Cited by10EIWOSBibtex

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

Junjun Li,David A Alvarez,Kiran V Chatty,Michel J Aboukhalil,Robert J Gauthier,Christian Russ,Christopher Seguin,Ralph Halbach

Singapore, pp.276-280E, (2006)

Cited by11EIWOSBibtex

Analysis ofFailure Mechanism on Gate-Silicided andGate-Non-Silicid ed, Drain/Source Silicide-blocked ESDNMOSFETsina65nmBulkCMOS Technology

Junjun Li,Kiran V Chatty,Robert J Gauthier,Christian Russ,Christopher Seguin,Ralph Halbach

(2006)

Bibtex

Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection

Junjun Li,Robert J Gauthier,Sushanta K Mitra,Christopher S Putnam,Kiran V Chatty,Ralph Halbach,C Seguin

(2006)

Cited by39Bibtex

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

Kiran V Chatty,Robert J Gauthier,Christopher S Putnam,Mujahid Muhammad,Min Hee Woo, Jituo Li,Ralph Halbach,C Seguin

(2005)

Cited by12Bibtex

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