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His group conducts research on the design, analysis, and implementation of self-timed systems. He is the recipient of twelve best paper awards, nine teaching awards, and was named to MIT technology review's top 35 young innovators under 35 for contributions to low power microprocessor design. His work includes the design and implementation of a number of self-timed VLSI chips including the first high-performance asynchronous microprocessor, the first microprocessor for sensor networks, the first asynchronous dataflow FPGA, the first radiation hardened SRAM-based FPGA, and the first deterministic large-scale neuromorphic architecture.
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IEEE Trans. Circuits Syst. II Express Briefsno. 3 (2024): 1683-1689
2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)pp.1-10, (2023)
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PROCEEDINGS OF THE 2023 THE 50TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, ISCA 2023pp.1006-1025, (2023)
CoRR (2023): 1-9
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Xiang Wu,Rajit Manohar
2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)pp.78-88, (2023)
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2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)pp.10-19, (2023)
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