Philip Jacob - Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute

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Scheduling for Clustered Vector Processors Near Memory

Arpith C. Jacob,Zehra Sura,Tong Chen,Carlo Bertolli,Samuel Antao,Olivier Sallenave,Kevin O’Brien,Ravi Nair,Jose R. Brunheroto,Philip Jacob,Bryan S. Rosenburg,Yoonho Park,Alexandre E. Eichenberger,Changhoan Kim

semanticscholar（2016）

引用0浏览0引用

Thermal Modeling of 3-D Stacked DRAM over SiGe HBT BiCMOS CPU

Ryan Clarke,Philip Jacob,Okan Erdogan,Paul Belemijian,Srikumar Raman,Mitchell R. Leroy,Tuhin Guha Neogi,Russell P. Kraft,Diana-Andra Borca-Tasciuc,John F. McDonald

IEEE access（2015）

引用4浏览0EIWOS引用

Reconfigurable 40 GHz BiCMOS Uniform Delay Crossbar Switch for Broadband and Wide Tuning Range Narrowband Applications

J. -W. Kim,M. Chu,P. Jacob,A. Zia,R. P. Kraft, J. F. McDonald

IET Circuits Devices & Systems（2011）

引用6浏览0EIWOS引用

Carry Chains for Ultra High-Speed SiGe HBT Adders

Alexey Gutin,Philip Jacob,Michael Chu,Paul M. Belemjian,Mitchell R. LeRoy,Russell P. Kraft,John F. McDonald

IEEE Transactions on Circuits and Systems I Regular Papers（2011）

引用9浏览0EIWOS引用

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

Michael Chu,Philip Jacob,Jin-Woo Kim,Mitchell R. LeRoy,Russell P. Kraft,John F. McDonald

IEEE Journal of Solid-State Circuits（2010）

引用66浏览0EIWOS引用

Correction to “a 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology”

Michael Chu,Philip Jacob,Jinwoo Kim,Mitch LeRoy, R.P. Kraft, J. F. McDonald

IEEE Journal of Solid-State Circuits（2010）

引用0浏览0引用

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks Simulations indicate that 3-D stacking of memory chips can overcome memory limitations on computer processing by allowing for faster clock rates or improved transfer of data and address information

Philip Jacob,Aamir Zia,Okan Erdogan,Paul M. Belemjian,Jin-Woo Kim,Michael Chu,Russell P. Kraft,John F. McDonald,Kerry Bernstein

msra（2009）

引用23浏览0引用

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Philip Jacob,Aamir Zia,Okan Erdogan,Paul M. Belemjian,Jin-Woo Kim,Michael Chu,Russell P. Kraft,John F. McDonald,Kerry Bernstein

Proceedings of the IEEE（2009）

引用95浏览0EIWOS引用

A 3-D Cache with Ultra-Wide Data Bus for 3-D Processor-Memory Integration

Aamir Zia,Philip Jacob,Jin-Woo Kim,Michael Chu,Russell P. Kraft,John F. McDonald

IEEE Transactions on Very Large Scale Integration (VLSI) Systemsno. 6 (2009): 967-977

引用21浏览0EIWOS引用

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