Peter Debacker

Peter Debacker (male) received the M.Sc. (Hons.) degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He worked with Philips as a system engineer and at Essensium as a System Architect before joining IMEC, Leuven, in 2011. A imec he is currently Program Manager in the Semiconductor Technology and Systems division and leads a team that researches semiconductor technology, architecture and algorithms to create efficient AI hardware ranging from DNN accelerators, to in-memory compute and neuromorphic hardware. Besides AI specific hardware, he works on power-performance-area (PPA) optimization of scaled CMOS technologies (for 3nm and beyond), emerging memories and beyond CMOS technologies. In his past he has worked on IMEC’s low-power digital chip and processor architectures and implementation in advanced technology nodes. His current research interests include AI, machine learning and neuromorphic computing, computer architectures, design methodologies, design-technology co-optimization, digital design and verification, sreliability, variability and low power design.