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I work on a large gamut of tasks related to timing analysis and verification. This includes SW coding of timing modelling and timing analysis engines, to timing model extraction, to timing closure work, and very specifically to timing related to external memory interface work.
In that regards, I have worked on creating calibrated algorithms that maximize the timing margins of high-frequency memory interfaces, and created timing modelling methodologies that take into consideration various types of effects including on-die margin loss, SI/PI and board optimization.
In that regards, I have worked on creating calibrated algorithms that maximize the timing margins of high-frequency memory interfaces, and created timing modelling methodologies that take into consideration various types of effects including on-die margin loss, SI/PI and board optimization.
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mag(2015)
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsno. 6 (2009): 874-887
DAC07: The 44th Annual Design Automation Conference 2007
San Diego
California
June, 2007pp.93-+, (2007)
Proceedings of the 43rd annual Design Automation Conferencepp.779-+, (2006)
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