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Some professional experience:
Founder and President, Aries Design Automation, Chicago, IL, May 2005 - present, where I lead R&D projects on formal verification topics for NASA, the U.S. Department of Defense, and the U.S. Department of Energy.
Adjunct Assistant Professor, Department of Electrical and Computer Engineering at the University of Illinois at Chicago, Chicago, IL, August 2006 - present: This is a part-time position that generally requires the teaching of one senior or graduate-level course per semester.
Visiting Assistant Professor, School of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, GA, 2002 - 2003: Taught a course integrating computer architecture and formal verification of microprocessors; advised graduate students.
Summer Intern, Motorola, Austin, TX, May - August 1998: Worked on the formal verification of the M.CORE microprocessor.
Ph.D. student in Electrical and Computer Engineering, Carnegie Mellon University, 1995 - 2001: Developed an Efficient Memory Model for behavioral abstraction of memory arrays in symbolic ternary simulation. This model was adopted by Intel, NEC, and Motorola in internal tools, by Synopsys in a prototype of a commercial tool, and by Innologic Systems in a commercial tool. Developed a tool flow and formal verification techniques that are highly automatic, and significantly outperform all previous methods for formal verification of pipelined microprocessors. This tool flow was used to formally verify a model of the M.CORE processor at Motorola, and detected bugs.
Technical Associate, Information Services, CS First Boston Corporation, New York, NY, 1994 - 1995: Worked on the development of a global information system.
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INTEGRATED FORMAL METHODS, IFM 2023 (2024): 193-213
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (2022)
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