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My main research objective is to develop the highest performance processor of a current generation, along with supporting memory systems, so as to reduce the completion time of a single computation task. Most of my research work focusses on achieving this goal with the use of instruction-level parallel (ILP) processing techniques that take advantage of rapidly changing technologies. These techniques include (i) the use of high-level control flow prediction and multiple flows of control to deal with control dependencies, (ii) the use of data value prediction and multiple instruction issue to deal with data dependencies, and (iii) the use of optimizing compilers to make best use of different microarchitecture features
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ITICSEpp.337-337, (2011)
Rania H. Mameesh,Manoj Franklin
PACTpp.421-430, (2010)
R. Mameesh,M. Franklin
Advances in Computer Science and Engineering (2010)
Rania H. Mameesh,Manoj Franklin
Proceedings of the 19th international conference on Parallel architectures and compilation techniques - PACT '10 (2010)
Austin, TXpp.223-232, (2008)
Speculative data distribution in shared memory multiprocessors (2008)
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Journal of Electronic Testingno. 1-3 (2008): 117-128
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