基本信息
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职业迁徙
个人简介
Research Interests
· High performance low power on-chip/off-chip interconnect analysis and optimization
· Interconnect centric design methodology
· Low skew low power clock network distribution and analysis
· Low power design
Education
Sept.2004 – Present Ph.D. Student, Computer Engineering, University of California, San Diego
Thesis Title: Low Power High Performance Interconnect Design and Optimization
Advisor: Chung-Kuan Cheng
Sept.2002 – Jul.2004 M.E., Computer Engineering, Tsinghua University, Beijing, China
Sept.1998 – Jul.2002 B.E., Electrical Engineering, Tsinghua University, Beijing, China
Research Experience
Sept.2004 – Present Research Assistant, University of California, San Diego, with Prof. Chung-Kuan Cheng
Research in on-chip and off-chip interconnect design and optimization, clock network
analysis, current-mode differential logic style design
Sept.2002 – Jul.2004 Research Assistant, Tsinghua Un iversity, with Prof. Tong Jing
Research in Standard cell global routing algorithms, crosstalk estimation and reduction in
global routing
Jul.2000 – Sept.2001 Research Assistant, Tsinghua University, with Prof. Yihe Sun
Logic design, logic verification, circuit simulation, layout design, and post simulation of a
Serial Code Generator
Teaching Experience
Sept.2008 – Dec.2008 Teaching Assistant, University of California, San Diego, for Prof. Ronald Graham
Teaching Assistant for undergraduate mathematics for algorithms and systems
Responsibilities included discussion session, office hours, homework solutions and exam
grading.
Mar.2008 – Jun.2008 Teaching Assistant, University of California, San Diego, for Prof. Tajana Rosing
Teaching Assistant for undergraduate digital system design laboratories
Responsibilities included lab designs, lab report grading, maintaining course website,
discussion session, office hours and exam preparation and grading.
Industry Experience
Jun.2006 – Sept.2006 Research Internship, clock synthesis group, Synopsys Inc., Mountain View, CA
Development of clock mesh synthesis and distribution algorithm
Jun.2005 – Aug.2005 Research Internship, EDA Lab, NEC Co., Kawasaki, Japan
Development of Clock planning system and link insertion algorithms considering process
variations
研究兴趣
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