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    My research group addresses fundamental problems in cache techniques and optimization for chip multi-processors. Currently I am also developing a simulator which is able to evaluate memory sub-systems quantitatively.

    Our simulator, called TSIM (Tsinghua SIMulator), is a fast and cycle-accurate memory sub-system modeling and evaluating framework for Chip Multi-Processors (CMPs). This simulator provides a flexible and extensible approach to evaluating architecture designs, models, and algorithms, including network-on-chip interconnection, cache hardware pre-fetcher, memory system protocol, replacement policy, etc.

    TSIM tries to balance among speed, accuracy and flexibility. By introducing the concept of statistical metamerics, TSIM separates the analysis stage from the simulation process. This provides a great facilitation for users to sample and analyze the performance metrics. More significantly, TSIM focuses on CMP systems and supports multithread workloads. A TSIM user is able to freely configure simulation parameters such as cache level, cache size, block size, number of cores, and the replacement policy.