Experience
    Education
    Bio
    Education: The University of Michigan, Ann Arbor, Michigan August 2001  Bachelor of Science in Engineering (Computer Engineering) Graduation: May 2004 GPA: 3.996/4.000  Master of Science in Engineering (CSE: Hardware) Graduation: May 2005 GPA: 8.111/9.000  Ph.D. in Engineering (CSE: Hardware) Conferred: April 2010 Thesis: “Disaggregated Memory Architectures for Blade Servers” Work Experience: Hewlett-Packard Laboratories, Palo Alto, California 2010-Present Post-Doctoral Researcher, Exascale Computing Lab, Manager: Parthasarathy Ranganathan  Exploring disaggregated memory architectures  Researching creating power- and cost- efficient server architectures for large-scale data centers University of Michigan, Ann Arbor, Michigan 2007-2010 Research Assistant, Advisor: Professors Steve Reinhardt and Trevor Mudge  Continued research on new system architectures for cost-conscious scale-out.  Exploring two-level, ensemble shared memory designs.  Researching processor design aimed at scale-out environments. Hewlett-Packard Laboratories, Palo Alto, California 2007-2010 Intern, Enterprise Software and Systems Lab/Exascale Computing Lab, Manager: Parthasarathy Ranganathan  Designed new disaggregated memory architectures for greater memory resource efficiency.  Developed new benchmarks for emerging scale-out environments.  Researched new system architecture design for cost-conscious scale-out using disaggregation.  Researching novel, ultra-dense low-power server form-factors. University of Michigan, Ann Arbor, Michigan 2004-2006 Research Assistant, Advisor: Professor Steve Reinhardt  Developed new, more modular out-of-order CPU model for computer simulator.  Researched simulation techniques to reduce simulation time.  Helped code infrastructure for simulator.  Worked on the M5 simulator, a full-system simulator using C++/Python.  Presented two tutorials on how to use M5 simulator. Advanced Micro Devices (AMD), Austin, Texas Summer 2005 Intern, Performance Evaluation Group, Mentor: Ravi Bhargava  Worked on simulator for next-generation AMD processor.  Implemented oracle branch prediction in simulator.  Implemented register checkpointing in simulator.  Ran performance limit studies. University of Michigan, Ann Arbor, Michigan Summer 2003 Volunteer Research Assistant, Advisor: Professor Mark Brehob  Researched existing standard and smart caching schemes.  Researched using stack distance probabilities towards a smart caching scheme. Teaching Experience: University of Michigan, Ann Arbor, Michigan 2006-2007 Graduate Student Instructor, Class: Engineering 100, Primary instructor: Professor Peter Chen  Led two to four undergraduate lab sections of 20 students each, held office hours.  Taught introductory level Verilog, digital logic, and assembly language. Publications:  “Hypervisor-based Prototyping of Disaggregated Memory and Benefits of VM Consolidation,” K. Lim, J. Chang, J. R. Santos, Y. Turner, T. Mudge, P. Ranganathan, S. Reinhardt, T. Wenisch, Poster at Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems, 2010  “Disaggregated memory for expansion and sharing in blade servers,” K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. Reinhardt, T. Wenisch, 36th International Symposium on Computer Architecture, June 2009  “Server Designs for Warehouse-Computing Environments.” K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt, IEEE Micro Top Picks, January 2009  “Understanding and Designing New Server Architectures for Emerging Warehouse Environments,” K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt, 35th International Symposium on Computer Architecture, June 2008  "The M5 Simulator: Modeling Networked Systems," N. Binkert, R. Dreslinski, L. Hsu, K. Lim, A. Saidi, S. Reinhardt, IEEE Micro, vol. 26, no. 4, pp. 52-60, July/August 2006 Honors:  ISCA 2008 paper recognized in IEEE Micro “Top Picks from Computer Architecture Conferences” (year’s 12 most significant research publications in computer architecture based on novelty and long term impact)  Recipient of Honorary Mention for EECS Outstanding Graduate Student Instructor, 2007  Angell Scholar, 2003-2004  Dean’s List, 2001-2003 Activities:  Program committee member, Sixth Annual Workshop on Modeling, Benchmarking, and Simulation, 2010  Chapter 5 exercises (Large and Fast: Exploring Memory Hierarchy) in Computer Organization and Design: The Hardware/Software Interface (4th edition), Elsevier, 2008  Reviewed submissions for MICRO, HPCA, IEEE Micro, TC, HiPC, JPDC Related Coursework: Parallel Computer Architecture, Microarchitecture, Computer Architecture, Computer Organization, Embedded Control Systems, Microprocessor Based Systems, Logic Circuit Synthesis, Digital Logic Design Computer Skills: Languages: C++, C, Matlab, Verilog OS/Platforms: Linux, Windows, UNIX