Jagmohan Singh received the B.Tech. degree in electronics and communication engineering from the National Institute of Technology Jalandhar, Jalandhar, India, in 2006, and the M.S. degree in electrical and computer engineering from the University of Texas at Austin, Austin, TX, USA, in 2013, with focus on discrete gate sizing for power optimization under performance constraints. Since 2013, he has been a Software Engineer with Cadence Design Systems, San Jose, CA, USA. From 2006 to 2011, he was with STMicroelectronics, Greater Noida, India. He was an Intern with Motorola, India, in 2005, and Advanced Micro Devices, Austin, TX, USA, in 2012. His current research interests include discrete optimization, algorithms, and automation for physical design of integrated circuits.