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Jaehoon Jang was born in Seoul, Korea, in 1969. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1991, 1993 and 1997, respectively. The subject of his doctoral thesis was about the improvement in efficiency of amorphous Silicon solar cell.
After receiving the Ph.D degree, he joined Samsung Electronics Corporation, Gyeonggi-do, Korea in 1997 and has been engaged in the development of devices and process integration for SRAM by April/2005. During that period, he has been working in the development of 8 M SP SRAM, 16 M DDR SRAM with 0.18 um technology and 8 M/16 M ultra-low power SRAM with 0.15 um technology and also, 8 M/16 M ultra-low power SRAM with 0.10 um technology. He was also one of the major developers of the revolutionary S3 SRAM. From May/2005 to April/2006, he has been a visiting scholar at Stanford University in Palo Alto, CA, USA. After returning to Samsung Electronics Co. Ltd., he has been involved in the development of 3-dimensionally stacked NAND flash memory up to now. His current interest is the development of sub-40 nm NAND cells for the stacked structure.
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IEEE Journal of Solid-state Circuitsno. 1 (2014): 334-+
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