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Patel’s research contributions include Pipeline Scheduling, Cache Coherence, Cache Simulation, Cache Data Prefetch, Multiprocessor memory modeling and analysis, Interconnection Networks, On-line Error Detection, Reliability analysis of memories with ECC and Scrubbing, Design for Testability, Built-In Self-Test, Fault Simulation and Automatic Test Generation. Patel is the inventor of the well known Illinois Cache Coherence Protocol and Illinois Scan Architecture, both are used heavily in most modern microprocessors. In addition, his Stride Prediction based Data Prefetch is the basis for nearly all data prefetch techniques used in most current microprocessors. Patel has supervised over 85 M.S. and Ph.D. theses and published over 200 technical papers.
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Springer Series in Reliability Engineering System Dependability and Analyticspp.429-430, (2022)
user-618b90cce554220b8f25959c(2018)
Special Computer Architectures for Pattern Processing (2018)
user-618b90cce554220b8f25959c(2015)
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