Now I'm a grown up and I work for Altera as a design engineer. At Altera, I work on timing modeling.
    My work/research is focused on field-programmable gate arrays (FPGAs). These are pre-fabricated programmable integrated circuits that are used in a wide variety of applications from large HDTV's to the machines that make up the backbone of the internet to some of the stuff they shoot up into space.

    At work, I help make the software that allows you to use these chips. Specifically, I work on understanding and modeling the performance of my company's FPGAs within the Quartus II software that is used to make designs on Altera's FPGAs
    In graduate school, my research focused on improving FPGAs by better understanding their limitations relative to one of their main competitors, application-specific integrated circuits (ASICs). One useful contribution from this work was that we actually measured the differences between FPGAs and ASICs in greater detail than had been done in the past. I also developed automated tools to help with things like transistor sizing to enable the exploration of trade-offs between cost and performance. During my Masters, I also used and developed automated tools to automatically design and layout an FPGA that was fabricated in 0.18 um CMOS. My supervisor for both my Master's and PhD was Jonathan Rose.