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My general research area is Computer-Aided Design (CAD) for Integrated Circuits. There is a continuous need to develop new CAD tools and design methodologies in order to keep up with the advances in Integrated Circuits (IC) technology and with the performance goals that are set for ICs. IC design is difficult, costly, and time consuming. It is not uncommon for the design of a large microprocessor chip to take 3 years, to require a team of about a 1000 designers, and to cost several hundred million dollars. As new generations of semiconductor technology become available, new problems arise in IC design, which require a next generation of CAD tools and methodologies. More information on the need for advances in design technology can be obtained from the National Science Foundation (NSF), the Semiconductor Industry Association (SIA), and from the Semiconductor Research Corporation (SRC). My work is focused on managing the design problems related to power dissipation, circuit timing and chip reliability. I have worked on issues related to average power (thermal concerns, battery life), chip leakage currents and power, as well as transient power (grid noise, metal reliability). Currently, my work is focused on chip power grid verification and reliability checking.
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Armen Kteyan,Valeriy Sukharev, Alexander Volkov,Jun-Ho Choy,Farid N. Najm,Yong Hyeon Yi,Chris H. Kim,Stephane Moreau
ISPD '23: Proceedings of the 2023 International Symposium on Physical Designpp.124-132, (2023)
Bijan Shahriari,Farid N. Najm
2023 24th International Symposium on Quality Electronic Design (ISQED)pp.1-8, (2023)
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user-5ef9583f4c775ed682ecca0f(2019)
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