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Deepraj Soni received the M.Tech. degree from the Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India, in 2012. He is currently pursuing the Ph.D. degree with the NYU Tandon School of Engineering, New York, NY, USA, where he works on hardware implementation, and evaluation and security of postquantum cryptographic algorithms.
His thesis focused on developing a framework for a hardware-software co-simulator and neural network implementation on an FPGA. After graduation, he worked as a Design Engineer in the semiconductor division of Samsung, Suwon, South Korea, and SanDisk, Milpitas, CA, USA. At Samsung, he was responsible for the design and architecture of image processing IPs, such as region segmentation and embedded CODEC. He also had charge of communication IPs, such as FFT/IFFT, time and frequency deinterleaving, and demapper for canceling noise. At SanDisk, he helped in the development of System-On-Chip level design for the memory controller.
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CoRR (2023): 272-282
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2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATEno. 99 (2023): 1-2
2023 IFIP/IEEE 31ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, VLSI-SOCpp.265-270, (2023)
2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)pp.1-6, (2023)
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