Chih-Feng Wu

Chih-Feng Wu received the B.S. degree from the National Yunlin University of Science and Technology, Yunlin, Taiwan, in 1995, the M.S. degree from National Central University, Taoyuan, Taiwan, in 1998, and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, Taiwan, in 2011. He is currently an Assistant Professor with the Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung, Taiwan. He was a consumer ASIC Designer with Holteck Semiconductor Inc., Hsinchu, Taiwan, from 1995 to 1996. He participated with the ADSL Transceiver Development Team of Computer, Communications Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, from 1998 to 2000. He jointed IC Plus Corporation in 2000. He was responsible for the design of the time-domain equalizer and the time-domain integration of ADSL transceiver chip with the Trendchip Technologies Corporation from 2001 to 2002, where he was the Technical Associate Manager with the Digital IC Department since 2002. From 2011 to 2012, he was involved in the physical-layer design of femtocell for 4G long term evolution with Information and Communication Research Laboratories (ICL), ITRI, Hsinchu, Taiwan. He held a post-doctoral position at National Chiao Tung University from 2012 to 2014, where he was responsible for the digital baseband communication algorithm and its related VLSI architecture for 60-GHz transmission system. He was an Adjunct Assistant Professor with National Taiwan Normal University, Taipei, Taiwan, and National United University, Miaoli, Taiwan, from 2012 to 2014. He was an Assistant Professor with the Department of Communication Engineering, National Penghu University of Science and Technology, Penghu, Taiwan, from 2014 to 2016. He was an Assistant Professor with the School of Information Science and Engineering, Fujian University of Technology, Fuzhou, China, from 2016 to 2017. From 2017 to 2019, he was involved in the physical-layer design of Automotive Ethernet in IC Plus Corp., Hsinchu, where he was the Senior Project Manager. His research interests include wireless/wireline communication systems, digital subscriber loop technologies, digital signal processing, carrier/timing synchronization and equalization techniques for FBMC, OFDM/DMT, and Automotive Ethernet systems, and the related integrated circuit design for the digital baseband inner transceiver.