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BS (CS), National University of Singapore, 1991。 BS (CS) with First Class Honors, National University of Singapore,1992。 MS (CS), National University of Singapore, 1996。 PhD (CS), University of California, Los Angeles, 1998。 My research interests lie in the general area of Computer Aided Design (CAD) for Very Large-Scale Integration (VLSI): Modeling and analysis of large-scale systems； Design of on-chip communications； Physical design and synthesis； Circuit design and synthesis。 Research Projects： Simulation of nano-scale transistors and wires (with Prof. Venkataramanan Balakrishnan, funded by NASA NCC 2-1363)。 Reliable Clock Synthesis (with Prof. Venkataramanan Balakrishnan, funded by NSF 9984553-CCR, NSF 0203362-CCR, PRF and DAC Scholarship for Douglas Lam)。 Interconnect-driven floorplanning (funded by PRF)。 Interconnect Planning and Synthesis of Physical Layout for Deep Submicron VLSI Design (funded by NSF 9984553-CCR)。 Noise-Aware Floorplanning and Global Routing (with Prof. Kaushik Roy, funded by Intel)。 Multiple-Voltage Placement (with Prof. Patrick H. Madden, SUNY Binghamton, funded by SRC Task 947-001) Logic and Physical Synthesis (funded by NSF 9984553-CCR)。 Reduced Order Modeling of RLC Networks (with Prof. Venkataramanan Balakrishnan, funded by PRF, SRC 99-TJ-689, and NSF 9984553-CCR)。 Operation and Monitoring of Power Grid with Dynamic Equivalents and State Estimation (with Prof. Chee-Mun 。Ong (PI) and Prof. Venkataramanan Balakrishnan, funded by Center for Security of Large Scale Systems)。 On-Chip RLC Interconnect Synthesis (with Prof. Kaushik Roy, funded by SRC 99-TJ-689) (completed)。 Publications： Jason Cong, Lei He, and Cheng-Kok Koh, ``Layout Optimization,'' Chapter 5.1 in Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet, NATO ASI Series, Kluwer Academic Publishers, 1997, pp. 205-265. Cheng-Kok Koh, Evangeline F. Y. Young, and Yao-Wen Chang, ``Global Interconnect Planning,'' Chapter 33 in Handbook of Algorithms for Physical Design Automation, ed. Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2009, pp. 645-672. J.-L. Huang, C.-K. Koh, and S. F. Cauley, ``Logic and Circuit Simulation,'' Chapter 8 in Electronic Design Automation: Synthesis, Verification, and Test, ed. Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Elsevier Inc., 2009, pp. 449-512. C.-K. Koh, J. Jain, and S. F. Cauley, ``Synthesis of Clock and Power/Ground Networks,'' Chapter 13 in Electronic Design Automation: Synthesis, Verification, and Test, ed. Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Elsevier Inc., 2009, pp. 751-850.