International Solid-State Circuits Conference

    International Solid-State Circuits Conference is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design to maintain technical currency, and to network with leading experts. It is held every year in February at the San Francisco Marriott hotel in downtown San Francisco. ISSCC is sponsored by IEEE Solid-State Circuits Society.

    Author Distribution

    Top Authors ( author's name : number of papers / citations )

    2015
    Wanyeong Jung: 1 / 47
    Dennis Sylvester: 1 / 47
    Seokhyeon Jeong: 1 / 47
    David Blaauw: 1 / 47
    Sechang Oh: 1 / 47
    Marleen Welkenhuysen: 1 / 14
    Srinjoy Mitra: 1 / 14
    Jan Putzeys: 1 / 14
    Cyriel M. A. Pennartz: 1 / 14
    Refet Firat Yazicioglu: 1 / 14
    Francesco Paolo Battaglia: 1 / 14
    Carolina Mora Lopez: 1 / 14
    Chris Van Hoof: 1 / 14
    Anantha Chandrakasan: 1 / 0
    Bram Nauta: 1 / 0
    2016
    Joel S. Emer: 1 / 790
    Tushar Krishna: 1 / 790
    Vivienne Sze: 1 / 790
    Yu-Hsin Chen: 1 / 790
    Refet Firat Yazicioglu: 6 / 110
    Chris Van Hoof: 4 / 109
    Dennis Sylvester: 6 / 105
    David Blaauw: 5 / 93
    Dongmyung Bae: 1 / 91
    Yeongjae Choi: 1 / 91
    Lee-Sup Kim: 1 / 91
    Jaehyeong Sim: 1 / 91
    Minhye Kim: 1 / 91
    Jun-Seok Park: 1 / 91
    Nick Van Helleputte: 3 / 60
    Long Yan: 4 / 58
    Kenichi Okada: 4 / 58
    Kaiyuan Yang: 2 / 55
    Piet Wambacq: 4 / 55
    Meng-Fan Chang: 3 / 54
    2017
    Hoi-Jun Yoo: 4 / 145
    Wim Dehaene: 2 / 135
    Stefan Sahl: 1 / 121
    Olov Haapalahti: 1 / 121
    Leonard Rexberg: 1 / 121
    Alberto Valdes-Garcia: 1 / 121
    Bodhisatwa Sadhu: 1 / 121
    Orjan Renstrom: 1 / 121
    Anders Carlinger: 1 / 121
    Daniel J. Friedman: 1 / 121
    Kristoffer Sjogren: 1 / 121
    Xiaoxiong Gu: 1 / 121
    Mark Yeck: 1 / 121
    Hakan Bengtsson: 1 / 121
    Yahya M. Tousi: 1 / 121
    Eric Westesson: 1 / 121
    Scott K. Reynolds: 1 / 121
    Gustaf Weibull: 1 / 121
    Joakim Hallin: 1 / 121
    Nadav Mazor: 1 / 121
    2018
    Hoi-Jun Yoo: 3 / 55
    Anantha P. Chandrakasan: 2 / 51
    Vladimir Aparin: 1 / 46
    G. Liu: 1 / 46
    J. W. Park: 1 / 46
    H.-C. Park: 1 / 46
    Y.-C. Ou: 1 / 46
    D. Lu: 1 / 46
    H. Hedayati: 1 / 46
    Jeremy D. Dunworth: 1 / 46
    T. Segoria: 1 / 46
    P. Monat: 1 / 46
    K. Chakraborty: 1 / 46
    Jongrit Lerdworatawee: 1 / 46
    B.-H. Ku: 1 / 46
    K. Douglas: 1 / 46
    A. Homayoun: 1 / 46
    Sanghoon Kang: 1 / 43
    Dongjoo Shin: 1 / 43
    Jinmook Lee: 1 / 43

    Publications

    Browse by Citation
    3

    7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication.Cited by 121

    Bodhisatwa Sadhu,Yahya M. Tousi,Joakim Hallin,Stefan Sahl,Scott K. Reynolds,Orjan Renstrom,Kristoffer Sjogren,Olov Haapalahti,Nadav Mazor,Bo Bokinge,Gustaf Weibull,Hakan Bengtsson
    (2017)
    21

    7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.Cited by 42

    Tomoharu Tanaka,Mark Helm,Tommaso Vali,Ramin Ghodsi,Koichi Kawai,Jae-Kwan Park,Shigekazu Yamada,Feng Pan,Yuichi Einaga,Ali Ghalam,Toru Tanzawa,Jason Guo
    (2016)
    25

    3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS.Cited by 36

    Karthik Gopalakrishnan,Alan Ren,Amber Tan,Arash Farhood,Arun Tiruvur,Belal Helal,Chang-Feng Loi,Chris Jiang,Halil Cirit,Irene Quek,Jamal Riani,James Gorecki
    (2016)
    41

    16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.Cited by 31

    Bruno Vaz,Adrian Lynam,Bob Verbruggen,Asma Laraba,Conrado Mesadri,Ali Boumaalif,John McGrath,Umanath Kamath,Ronnie De La Torre,Alvin Manlapat,Daire Breathnach,Christophe Erdmann
    (2017)
    50

    13.3 A 56Gb/s W-band CMOS wireless transceiver.Cited by 28

    Korkut Kaan Tokgoz,Shotaro Maki,Seitaro Kawai,Noriaki Nagashima,Jun Emmei,Masato Dome,Hisashi Kato,Jian Pang,Yoichi Kawano,Toshihide Suzuki,Taisuke Iwai,Yuuki Seo
    (2016)
    54

    4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing.Cited by 27

    Tomohiro Yamazaki,Hironobu Katayama,Shuji Uehara,Atsushi Nose,Masatsugu Kobayashi,Sayaka Shida,Masaki Odahara,Kenichi Takamiya,Yasuaki Hisamatsu,Shizunori Matsumoto,Leo Miyashita,Yoshihiro Watanabe
    (2017)
    60

    A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.Cited by 26

    Wei-Hao Chen,Kai-Xiang Li,Wei-Yu Lin,Kuo-Hsiang Hsu,Pin-Yi Li,Cheng-Han Yang,Cheng-Xin Xue,En-Yu Yang,Yen-Kai Chen,Yun-Sheng Chang,Tzu-Hsiang Hsu,Ya-Chin King
    (2018)
    67

    4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAMCited by 24

    Tsutomu Haruta,Tsutomu Nakajima,Jun Hashizume,Taku Umebayashi,Hiroshi Takahashi,Kazuo Taniguchi,Masami Kuroda,Hiroshi Sumihiro,Koji Enoki,Takatsugu Yamasaki,Katsuya Ikezawa,Atsushi Kitahara
    (2017)
    92

    11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology.Cited by 21

    Ryuji Yamashita,Sagar Magia,Tsutomu Higuchi,Kazuhide Yoneya,Toshio Yamamura,Hiroyuki Mizukoshi,Shingo Zaitsu,Minoru Yamashita,Shunichi Toyama,Norihiro Kamae,Juan Lee,Shuo Chen
    (2017)
    96

    10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.Cited by 21

    Amin Shokrollahi,Dario Carnelli,John Fox,Klaas Hofstra,Brian Holden,Ali Hormati,Peter Hunt,Margaret Johnston,John Keay,Sergio Pesenti,Richard Simpson,David Stauffer
    (2016)